I'm surprised that you can't power the error amp and buffer from a higher supply than 1.3V. Usually depending on battery technology(Li-Ion) you get a minimum of 2.5 V and the 1.3 V would only be used at the source of the PMOS power fet to reduce power dissipation on chip and improve efficiency. By the way, 1.3 V is pretty low headroom for the PMOS power fet over temperature, process corners and load current. I would ask for clarification about this VIN=1.3 V spec first. You may need an NMOS LDO for these very low VIN level if the load current is very high.
With 0.8 V reference and VIN=1.3 you can't use NMOS inputs or PMOS inputs. You would need to have low-vt NMOS devices.
The buffer needs to be rail-to-rail input/output to turn-off the fet during no-load conditions and hot temp with fast(strong) P. Your only other choice is to drive the gate of the PMOS power fet directly from the error amplifier and figure out a slew-rate boost circuit to drive the fet. Your AC loop characteristics would then be mostly dominated by the Cgd of the PMOS power fet which ties your hands to get PSRR over bandwidth.

The rail-to-rail buffer needs to be wide bandwidth or else you're not going to able to stabilize the system. I would keep the buffer one-stage of gain and use other circuit techniques that will improve the output swing of a simple folded-cascode. You're driving a gate capacitance so you don't really need a two stage.
This kind of design gets interesting due the load current dynamic bandwidth requirements vs. efficiency. If you can clarify specs first to see if you really need to design something this fancy that would be the best way to go.
I've designed this things many times before, for the right price i can do it for you.
Good luck.

Raul wrote on Oct 5^th, 2006, 2:57pm:



it's not my idea, it's just specification. it is used in a system which regulates its vdd itself to reduce power loss