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email_gz Junior Member Offline Posts: 31 gaoz.mail@gmail.com	Why Sigma Delta Modulator for Frac N can OverLoad? Sep 05^th, 2006, 7:48pm Dear All: I think that SC Sigma Delta Modulator for AD OverLoad because quantizer overload and SC integrator output swing limited and then SNDR drop. Are these right? But why Digital Sigma Delta Modulator for Fraction N Divider can OverLoad,and then SNDR drop? thank all very much
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rf-design

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Reiner Franke

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Re: Why Sigma Delta Modulator for Frac N can OverL
Reply #1 - Sep 7^th, 2006, 11:04pm

There could be 2 reasons:

1. The noise shaping filter does not have the right number of bits in each register or numeric stage. So wrap over clip happen for some situations.

2. If the order of the sigma-delta is higher and a multi-modulus divider is used the number distribution could approach the division range. So the number distribution get clipped from one side. That impact the noise shaping.

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timmc6

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Re: Why Sigma Delta Modulator for Frac N can OverL
Reply #2 - Sep 9^th, 2006, 4:21pm

I am currently design a digital Sigma Delta for a Frac N PLL and I saw that if the accumulator size is not large enough, there will be an error when it tries to wrap around. For example, if your required MOD value is 128, and you have a 3rd order MASH architecture, it is possible that the last accumulator will need to hold a value of 256. So the required accumulator size would be 8 bits instead of 7 to hold a maximum value of 256. If 7 bits are used and the accumulator needs to hold something larger than 128, it will wrap around and not generate a carry, throwing off the whole SD operation. Hope this helps.

Tim

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email_gz

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Re: Why Sigma Delta Modulator for Frac N can OverL
Reply #3 - Sep 10^th, 2006, 6:41pm

thank rf-design, timmc6 very much ! Your answers are very helpful to me ! But I still have some puzzles.
Does the accumulator wrap around mean that the adder output is overflow? Is this equivalence quantizer overload?
Does The digital Sigma Delta for a Frac N PLL operate in 2's complementary binary code or in unsigned binary code ?
If we use the adder's carry bit to control the MMD, so the average output approach our Fractional divider target. For a 7 bit unsigned adder has 7 bit unsigned input , 8bit unsigned output(MSB is carry bit), so I think the 8bit result can guarantee holding a value of 256, and the MSB carry bit can control the MMD.

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