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kiran123

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D-CAP using NMOS and PMOS
Sep 05^th, 2006, 11:46pm

Hi Experts,
Herewith i have attached a DECAP arrangement using NMOS and PMOS
i have a few following doubts on this

1) what is the operating region of both transistors (NMOS and PMOS)
2) how could i realise total capacitance from VDD to VSS interms of MOS capacitances(Cgs,Cgd,Cgb...etc)
3) what are the specific advantages of this over our conventional NMOS cap or NMOS in NWELL cap?

Any help on this highly appreciable as it helps us lot

Thanks
Kiran

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cap_pic_001.JPG

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Geoffrey_Coram

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Re: D-CAP using NMOS and PMOS
Reply #1 - Sep 6^th, 2006, 6:46am

kiran123 wrote on Sep 5^th, 2006, 11:46pm:

1) what is the operating region of both transistors (NMOS and PMOS)

I would say both transistors are in strong inversion (and in the linear region). The channels will conduct (at least slightly, initially, and then better as time goes on) such that the gate of the NMOS will eventually be pulled up to VDD and the gate of the PMOS will be pulled down to VSS.

Once the gates have settled out, the channel resistances will be small, and you can probably ignore them when computing the capacitance, which will simply be the total gate capacitance (cgs+cgd+cgb, including overlap caps) for the two devices.

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kiran123

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Re: D-CAP using NMOS and PMOS
Reply #2 - Sep 6^th, 2006, 10:39pm

Geoffrey,
thanks for your comments on this topic , actually i did DC simulations on this and understood that (Wp = 2*Wn where as Ln=Lp) our simulation results are telling the same.

when i checked the gate voltage of both transistor Vg(PMOS) = 0V and Vg(NMOS) is VDD so both are in strong inversion.

I also checked connecting both transistors in parallel such that PMOS is in ON and NMOS is in ON condition now overall cap is same as that of total cap between VDD and VSS of figure.
here one point attacted our attention is for the taken Wp, Wn ,Lp and Ln as i listed above from the experiment of NMOS and PMOS parallel view the typical values of caps are as listed below

NMOS cap (Wnand Ln) = 0.13f
PMOS cap (Wp and Lp) = 2.0f
total cap either in parallel or of the figure given before is = 2.2f

so conclusion is that for a given area PMOS is giving more CAP value than that of NMOS

this what making me wonder as i have not come across any official docs or papers suggesting PMOS gives better cap ?
providing information on this really helps to know which is good CAP and why?

Best Regards
Kiran

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: D-CAP using NMOS and PMOS Reply #3 - Sep 7^th, 2006, 8:51am Well, if the PMOS has a lower mobility, then maybe the threshold voltage was set lower such that it has more inversion charge so the id_sat is the same as NMOS for a given gate voltage. With more charge, you get more capacitance ... ?
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kiran123

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Re: D-CAP using NMOS and PMOS
Reply #4 - Sep 7^th, 2006, 10:31pm

If you are aking about that Vt model settings i don't have awarenes but from simulation front what i understood taken Wn and equivalent Wp i found P-MOS cap is giving better (more CAP) than an N-MOS realised cap

this makes me wonder if this is case so why not PMOS is used for CAP where we want higher CAP value /given area ? and unfortunately i have not come across any docs or papers on this these factors makes me to conclude what are the disadvantages that this kind of CAP?

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kiran123

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Re: D-CAP using NMOS and PMOS
Reply #5 - Sep 7^th, 2006, 10:33pm

If you are aking about that Vt model settings i don't have awarenes but from simulation front what i understood taken Wn and equivalent Wp i found P-MOS cap is giving better (more CAP) than an N-MOS realised cap

this makes me wonder if this is case so why not PMOS is used for CAP where we want higher CAP value /given area ? and unfortunately i have not come across any docs or papers on this these factors makes me to conclude what are the disadvantages that this kind of CAP has?

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