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grosser

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power transitor leakage
Sep 06^th, 2006, 5:16am

hello

i mean about LDO circuit again

how can i decrease power transistor's (PMOS) leakage under 5uA and under what conditions i should measure it?

I do that with the lowest Vdd and no load in every process corner.

Trasnsitor has to be large to drive 100mA load under 1.3V so i cannot decrease its width much. It's 15mm wide nad 0.35um

regards

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loose-electron

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Re: power transitor leakage
Reply #1 - Sep 6^th, 2006, 9:11am

Hey there:

Leakage tends to be worse at higher temperatures, so I would go to your hot corner, and start by looking there.

If this is gate leakage, and getting to zero leakage is important to you, you may want to consider using the I/O transistors, usually higher threshold voltage but thicker gate oxides and less leakage.

Jerry

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Jerry Twomey
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Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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grosser

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Re: power transitor leakage
Reply #2 - Sep 6^th, 2006, 9:17am

loose-electron wrote on Sep 6^th, 2006, 9:11am:

Hey there:

Leakage tends to be worse at higher temperatures, so I would go to your hot corner, and start by looking there.

If this is gate leakage, and getting to zero leakage is important to you, you may want to consider using the I/O transistors, usually higher threshold voltage but thicker gate oxides and less leakage.

Jerry

isn't that drain current under no load conditions??

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: power transitor leakage Reply #3 - Sep 7^th, 2006, 9:05am You have several different mechanisms happening here. If I remember correctly they all get worse at higher temperatures.
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Raul

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San Jose, CA.

Re: power transitor leakage
Reply #4 - Oct 10^th, 2006, 2:34pm

Power transistor leakage will be worse under fast-P(for PMOS LDO) corner and hot. Design wise all you can do is to design a circuit that under no-load conditions will drive the gate of the PMOS all the way to supply(at least within 60 mV of the supply rail given the device in sub-threshold conduction). Some people go through the trouble of building a charge pump and connecting the body of the pmos to a voltage that is higher than the supply to increase the VT of the PMOS with the body effect. This will inject noise to the output of the LDO and cost you caps for the charge pump which doesn't really need to drive much current at all.
There is really nothing else you can do circuit wise since this is a device physics problem. Everyone has this problem, talk to the fab and see what they can do for you.

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regards, Raul Perez

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