I'm a newbie to the verilog language. I would like to explain my problem with a C program example:
main()
{
int i;
for(i=0;i<3;i++)
{
static int a=1,b=2,x=0,y=1;
add(a,b);
a++;b++;
mul(x,y);
x++;y++;
}
}
add(int,int)
{
statements;
}
mul(int,int)
{
statements;
}

Here we can see that the functions add() and mul() are called for every iteration and also  their parameters are updated and passed for every iteration....

Now my problem:

I have two sub-modules in main module(top-level). I need do to the iterations for 5 rounds...So can you please tell me how can I do the iteration and at same time passing the parameters into the sub modules...

Hope you understood the problem...Hoping for the positive response..

Thanks a Ton.

Regards,
Raghu

Your code doesn't show what you want to do with the results of adding and multiplying.

Does the result of one iteration get overwritten by the result for the next?

You can't pass the values in as parameters.  Maybe as wires?  Seems more a digital Verilog question, not really AMS (though, of course, digital is a subset of AMS).

-Geoffrey

I still don't understand what you are trying to do.  What happens with the arithmetic results?  (Why do the loop, if you only want the last values?)