2raghu
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Posts: 2
India
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I'm a newbie to the verilog language. I would like to explain my problem with a C program example: main() { int i; for(i=0;i<3;i++) { static int a=1,b=2,x=0,y=1; add(a,b); a++;b++; mul(x,y); x++;y++; } } add(int,int) { statements; } mul(int,int) { statements; }
Here we can see that the functions add() and mul() are called for every iteration and also their parameters are updated and passed for every iteration....
Now my problem:
I have two sub-modules in main module(top-level). I need do to the iterations for 5 rounds...So can you please tell me how can I do the iteration and at same time passing the parameters into the sub modules...
Hope you understood the problem...Hoping for the positive response..
Thanks a Ton.
Regards, Raghu
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