Hello,

I am using AMS through cadence's latest ADE and am having trouble instantiating a verilogAMS module in another verilogAMS module. I know the syntax of how to do it code, but the elaborator gives me an error:

ncelab: *E,CUCFUN: instance 'f1' of the unit 'dff_va' is unresolved in '\test .stage:veriloga'.

So I'm instantiating f1 like this: dff_va f1(...). The verilogAMS modules dff_va and stage are in the same library.

Is there some seperate syntax to include a module, or does AMS have some other way of including modules?

Any help would be appreciated.

Thanks,
Xter

I had the same error on friday, i forgot to include the library, where the module is that needs to be instantiated, in the library list in the hierarchy editor  ;)