If you use an asynchronuous divider the phase jitter of the individula stages accumulate. Typical in CML there is also current scaling for the stages operating at lower frequencies. These contribute more to the output jitter of the critical edge. A way to avoid this accumulation is to use a noise optimized register to resynchronize the last noisy edge with the input clock.

Be careful with delay issues! If the noisy edge to synchronize is in the critical register window you can have undefined output states.