chase.ng
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penang/malaysia
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Hi all,
It appears to me that most high speed CMOS OTA like the one utilized in pipeline ADC (sampling rate > 100MHz) are usually implemented as single stage OTA such as folder cascode coupled with other tricks like gain boost, rather than 2-stage. My understanding is that compensation cap in the 2 stage structure will slow down the speed regardless of what kind of compensation is being used and therefore more power needs to be burned to increase the speed. I try to design some high speed 2 stage OTA before, but I found that at some point, burning more power will not really increase the speed without compromising the stability, I think that has something to do with the parasitic capacitance.
Is anybody here experienced in designing high speed OTA? Especially 2 stage OTA. I would really appreciate if someone can share his/her experience on the design, such as what is limitation? How fast (in terms of gain bandwidth product or unity gain frequency) can an OTA given a particular process?
Thanks and Regards, chase
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