In my comparator design, the spec for bandwidth is very high or the absolute delay from datain to dataout is very less. To acheieve this I ended up using minimum channel length of the devices. Now running the dc sweep simulation for offset I am getting very low offset value. and running statistical tool for offset and looking its 3sigma value is well within the specs and it hard to believe on the results.
Now my concern is: is there simulation to silicon mismatch OR the process is still not matured? because text book (common theory) says that lesser channel length will result higher offset.

Also, apart from DC sweep method of calculatiing offset, what if I give one of the input as Vref (reference voltage) and the other one as very slow rising/falling signal (say 1v/ms) and see how the output is toggling in transient response? Hence calculate the offset. Whether this method is more accurate? If so, why?

-Bharat

it is true for "less device, less mismatch". consider the layout and tapeout if using less dimension device the comp will suffer from matching-problem. there is tradeoff between speed and offset.

regarding of offset simulation the dc and slow tran sweep will get the same results. but the tran must be very very slow. basically the dc is the first choice.