cr
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Hi All,
I'm currently tasked with getting a few control gates working in our Verilog-A system simulations and unfortunately AMS is not currently an option. I have a strong Verilog-D background, have read most of Ken's book and have looked at a lot of the online models and the ones supplied by Cadence. What I am having a problem with is understanding why the Cadence models are written the way they are. The following pattern is used to detect the input transitions:
logic_input = V(vlogic_in) > vthreshold; @(cross(V(vlogic_in) – vthreshold, 1)) logic_input = 1; @(cross(V(vlogic_in) – vthreshold, -1)) logic_input = 0;
What I don't understand is why the “logic_input” (an integer) is being set by both the conditional and the event? I do understand that you want to use some form of cross to more accurately detect transitions.
Any help in expanding my understanding is most appreciated!
C.
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