Quote:If I would like to synthesize this SA register model directly to layout, is there a way to do that?
What do you mean with synthesis in this context?
Synthesis usually means you have described your circuit
in a Verilog or VHDL on Register Transfer (RTL) abstraction
level and synthesize it to Gate level. Therefore you also need
a standard cell library as reference for the synthesis tool.
http://www.doulos.com/knowhow/verilog_designers_guide/synthesizing_verilog/Does this answer this question?
Quote:Also, does spectre simulate verilog code?
No, just VerilogA. There are specific Mixed-Signal Simulators
which are able to simulate both transistor level and digital
as well as mixed signal HDL.
Bernd