Hi Guys,

Given the standard deviation Sigma value (say 0.1%) of the matching for two capacitors, which have the same drawn size (say 10um * 10um),
when I want to get ratio of 4 by drawing five (4 vs 1) the same size capacitors (10um *10um),how can I determine the standard deviation Sigma value for this situation? Will the matching be improved or decreased?

It is said that in a pipelined ADC, DNL improves by square of 2 with every extra bit of resolution in the first stages, but why?  Because this will improve the matching in the first stage, but how?

Yawei

ywguo wrote on Oct 19^th, 2006, 10:27pm:


I sure wish someone would write a good tutorial on this stuff -- actually, I wish publishers would realize the need, as they reject the papers  ::)...

For the matching of the N:1 case you need to consider each device individually.  To do this you divide the matched pair standard deviation by √2.  Assuming σ = 0.1% is the standard deviation of the pair of 1x devices, the standard deviation of the 1x device is (0.1%)/√2.  Since σ decreases by square-root area, the standard deviation for the Nx device is ((0.1%)/√2N).  Finally, the variance for the 1x device paired with the Nx device is
σ^2 = ((0.1%)/√2N)^2 +  ((0.1%)/√2)^2, which gives you your answer if N=4.

Note that for N=1, σ = 0.1%, which was the original assumption.

The matching is dominated by the small device.  This becomes problematic if you want to make a large ratio.

You might be able to gleen something along these lines from my 2004 CICC Paper... then again, it may be far enough off topic to confuse you more.

rg

Hi,

I am sorry that I make a typo in the question.

Quote:


It should be DNL improves by square root of 2 with every extra bit of resolution in the first stages.

The reference is Wenhua Yang, et al., A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input, JSSC, Dec. 2001.


Best regards,
Yawei

Hi Yawei,

sqrt(2) improvement makes sense in terms of matching. I was wondering why you mentioned 2^2 earlier,
and hence asked for the reference. I think Rob has clarified this point quite well by explaining how it works.
I have 1 more points on similar lines to suggest:

The matching is important only when looking at the DAC feedback term in the MDAC output

Vout=2^n.Vin - Gdac.Vref

as the Gdac term is the only one which introduces DNL. If you assume a standard MDAC scheme, then
there are 2^n-1 capacitors which comprise Cs, and 1 capacitor which comprises Cf. Now, Gdac is
realized by the combination of multiple unit caps. Hence, the mismatch terms are being combined
and assuming uncorrelated mismatch between the various caps, the overall error can be expected
to go down in a sqrt() fashion. Does this make sense? It is also worth noting that if you are comparing
2 different MDACs with different number of bits resolved in the stage, then you assume that the unit cap
is the same for both in order to get this result.

Regards
Vivek


ywguo wrote on Oct 22^nd, 2006, 9:53pm:

ACWWong wrote on Oct 21^st, 2006, 1:51pm:


Yes, except bottom plate parasitics and the floating node can really mess you up.  If you can get around that, it is the best way.  It works great for resistors.