Hi Experts,

 I tried to measure SSN in MDL mode here i am bit confuse about the results that i got using this method, First let me explain the method that i use to measure it

as shown in CKT_SSN i have used the 8 no.of buffers each are similar and drive capacity of 12mA at VOH and VOL which are connected between VDDS and VSS by their VDDS_IN and VSS_IN pins, so that i can unclude package paracitics of Power and Gnd pins

the mdl file contains below lines of code
/***************************************/
alias measurement NOISE {                                                                                
   export real Power_dip,  Ground_dip, VIH , VIL
   run Tran
   Power_dip  = min(V(VDDS_IN))  
   Ground_dip = max(V(VSS_IN))

   VIH  = VH*0.7
   VIL  = VH*0.3
}
run NOISE
/***************************************/
VH = VDDS

so that my aim is Power_dip > VIH , Ground_dip < VIL

but it is not meeting spec means Power_dip is close 0V and Gnd_dip ~VDSS

so alternatively i removed the output stage and connected a simple small inverter. Now ckt has max transistor width is < 10u (includes all stages of buffer). Using this when i tried to simulate still i am getting the almost (means comparatively bit improvement but not meeting spec and worst). I have theoritically no clue why still it show this much value (basically this noise contributed by mainly output stage because of husge transistors , so if i reduce that transistors size to very very low value why am i still see this senario)

Can anybody let me know the approach of doing this is fine towards SSN estimation , any practical approach or docs help me


Thanks in Advance for your support
kiran

Attached the file