Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Aug 25
th
, 2024, 9:15pm
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Simulators
›
RF Simulators
› question about PA's load-pull matching
‹
Previous topic
|
Next topic
›
Pages: 1
question about PA's load-pull matching (Read 3009 times)
dragonnj
New Member
Offline
Posts: 6
question about PA's load-pull matching
Oct 26
th
, 2006, 7:17pm
Hi,all
I am a graduate major in RF PA design. I used the cadence spectreRF to sim load-pull matching. I followed the user guide to matching the output of PA. I just wonder how to check the results of my matching if it is correct.
Just like the conjugate matching, when it is well matched that S22 should below -12dB. I wonder if there is a standard like the conjugate matching to check the load-pull matching.
Does anyone can give me some advice?
Thanks a lot!
---Jackey
Back to top
IP Logged
ACWWong
Community Fellow
Offline
Posts: 539
Oxford, UK
Re: question about PA's load-pull matching
Reply #1 -
Nov 6
th
, 2006, 3:15am
I don't think a standard exists other than your own specifcations for output power, harmonic levels, efficiency etc. over your frequency of interest. If you meet/optimise your specs, then the load pull matching is complete.
Back to top
IP Logged
dragonnj
New Member
Offline
Posts: 6
Re: question about PA's load-pull matching
Reply #2 -
Nov 6
th
, 2006, 10:33pm
thank you ACWWong!
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
»» RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.