I am beginning the research on weak capacitive  signal pickup circuits design. I my research work I need generate a time-variable capacitor (Cs in the figure below) in Cadence and simulated it using Spectre.Cs is changing its capacitive value in a frequncy of 1kHz.

I have tried making a Cs using VerilogA language. But this can only generate varible current and is not fit my usage.
Recently I find a paper about 'variable capacitor '. But it is described in Pspice. I really want to kown if it can also used in Cacence Spcetre and how to do it.

 Can you give a suggestion about it?

Try reading http://www.designers-guide.org/Modeling/varactors.pdf.

-Ken