douglas
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Hello everybody,
time ago I used to make some verilogams codes. I've been inactive for a while and I've lost the practice.
now I'm trying to make a code, but totally digital (and using verilog hdl). the point with verilogams is that I'm trying to use something from it in my verilog-hdl code but I don't get it to work.
let me explain, its easy but I just can get it:
I have an ENABLE signal. when ENABLE goes high, an ouput clock must start (with a defined period). when enable goes down, this clock must goes to zero and stay at zero.
in verilog ams I could use the always block without a sensitivity list, for example:
always if (V(ENABLE)) Clk = ... else Clk = ...
but in HDL I can't. the main problem Im having is stopping the Clk when Enable goes to zero. if somebody can give me a tip or tell me what Im doing wrong I would be very grateful.
this is what Im doing:
reg Clk; initial Clk = 0; parameter delay = ... parameter period = ...
always @(VLOEN) if (VLOEN==1) begin #(delay) Clk <= 1'b1; //some delay forever begin: COUNTING #(period * 0.5) Clk = ~Clk; if (VLOEN==0) disable COUNTING; end end else if (VLOEN==0) Clk <= 1'b1;
I Thanks in advance.
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