Hi,

I want to design to a macromodel with components like capacitors ,resistors to emulate a device. So that i can use it like the VCVS as used for running opamp based simulations.

I would like to know the way to create the macromodel and then use it.

Thanks in advance.

hi,

I actually want to calculate a capacitance value based on the voltages given to its terminals. I have done this in SPICE.
I was using V(node1, node2) to get the voltage and calculate the capacitance values using an expression.
In spectre, I am unable to do the same thing. I am getting an error.

Is there a better way to use voltages in expressions.

Thanks in advance.

RE

I agree entirely with Ken in this specific case, but it is possible to formulate voltage dependent capacitors (preferrably using a charge-based approach) using the "bsource" component in spectre. This is internally implemented in Verilog-A, and allows voltage or current dependencies to be expressed using spectre syntax.

See spectre -h bsource for more details, or look in the documentation.

However, Verilog-A is a good thing to learn and have under your belt - it gives you far more flexibility than bsource does. Ken and Olaf's book The Designer's Guide to Verilog-AMS is a good place to start on this.

Regards,

Andrew.