stumcn
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I'm fairly new to Verilog myself but I think(!) I can answer your questions.
Question 1 & 2.
The initial_step event will occur, naturally enough, at the first point of the simulation, ie 0s. Similarly, final_step will trigger an event at the last available point of the simulation.
Question 3.
The line V(out) <+ transition(n ? vh : vl, 0, tt); contains a conditional operator. Ignore the transition statement and look simply at V(out) <+ n ? vh : vl;. This means that if condition n is true (i.e, '1') then V(out) will equal vh; if not true, V(out) will equal vl. I'm assuming here that it's not the transition statement your querying but the operand within that statement.
Finally, about the syntax of timer(start, period).
This means the event will occur at 'start' and will repeat itself at multiples of 'period'. If 'period' is not specified, as in this case, then the event will only be triggered once at the time specified by 'start'.
I'm sure it could be explained more clearly than I've put it but I hope that helps.
Stu
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