junaidgill
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Posts: 2
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hello, i am new to verilog-a and i am trying to write code for NAND gate. can anyone please help me to complete the behvior:
module NAND(in1, in2, out)
inout in1, in2; output out; electrical in1, in2, out;
parameter real vlogic_high = 3.5;
//behvior of NAND GATE (i need help in this part)
endmodule
i know that i should make use of @(cross(V(in1) - thresh, +1)) but i don't know the correct way.
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