Hi,

I have verilogA code that works when run in cadence spectre, but not in Hspice. It's included as a subckt.

I) In attempting to debug this problem, I commented out everything except the port definitions. The code is saved in a file called stage5.va:

`include "constants.vams"
`include "disciplines.vams"

module p_stage3_calib_model(VDD, Ph1, Ph2, Vrefp, Vrefn, Vip, Vin, D0M, D0L, S1, S0, Vop, Von);
     input Vip, Vin, Ph1, Ph2, Vrefp, Vrefn, VDD;
     output S1,
     output D0M, D0L;
     output Vop, Von;
endmodule;

II) The instantiation looks like this:

yistage5 vdd1 Q1 Q2 vrefp vrefn vo6_p vo6_n d5l d5m SwitchRefHiStg5 SwitchRefLoStg5 vo5_p vo5_n p_stage3_calib_model

III) In the .lis file, the error reads like this:

    During .hdl command processing, loading Verilog-A modules from
       './stage5.va'.
hsp-vacomp:
hsp-vacomp: Invoking the Verilog-A compiler for 'stage5.va'

** error **
During Verilog-A Device processing:
   Failed to compile the Verilog-A File,
       'stage5.va'.

IV) And at the command prompt, I get this error:

ARnow: Undefined variable.



I am out of things to try to debug this problem. I thought if I slowly worked through the code, I could isolate this undefined variable, but I took out everything, and still get it.

Anyone have this error before?

Thanks!
Xter

Hi,

1. The comma is a typo from the paste. It is a semi-colan in code.

2. I did switch it to x.. as the instance name, same error. [The reason I left it as y... was because I netlisted in HspiceD in analog design environment, and used that netlist. I figured if it was automatically netlisted then there would be less errors introduced by me.]

Is there perhaps a version of hspice I should be using? I am currently using VY-2006.09 on a linux machine.

Thanks,
Xter