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eng

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Output impedance matching LNA 400MHz
Nov 25^th, 2006, 8:10pm

Hi,
I'm working on an LNA design around 400MHz in 0.18um process with Cadence spectreRF. Besides some other topologies right now I'm focused source degenerated single ended cascode LNA. I have couple questions:

1) It is written in most of the papers/books (i.e. Tom Lee's book) that the drain inductor should be used to tune out the capacitance at the drain node of inductor (plus the one coming from the mixers input). So this will act as second frequency determining circuit along with the input matching network for the LNA. However at this frequency the inductor value to tune out those capacitance is huge for an on-chip one. Is it necessary to tune out all the capacitance? What are the considerations to select the drain inductor value?

2) Since the LNA will be followed by a mixer it doesn't need to be matched to 50 ohm. In this case should I still place a 50 ohm port in the schematic to simulate the s parameters and NF P1-dB IIP3 etc.? Is 50 ohm port going to give me the right simulated results?

Thanks in advance.

Best Regards
eng.

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ACWWong

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Re: Output impedance matching LNA 400MHz
Reply #1 - Nov 26^th, 2006, 4:15am

Hi eng,

my comments are:
1) Yes, usually you want to reasonate out the load capacitance to provide maximum impedance... this is because the gain in the LNA is proportional to this output load impedance. So in direct answer to your query, No, it is not necessary to tune out all the capacitance, all you want to do is maximise the load and hence gain.
Usually in an LNA you want to use as big an L value as you can in the load to maximise the gain. On chip L in 0.18CMOS with a good thick top metal should enable to get >30nH in say 300um^2 with Q of maybe 4 at 400 MHz at a first guess... this is only about 300 ohms if tuned.. you might consider padding the load with well defined MIM cap so that parasitics C's don't dominate any 1/sqrt(LC) reasonce you are looking for.
But I would recommend looking at using a load resistor (if you can tolerate IR drop)... say if you used 1k load resistor, you could tolerate 400fF of load C (parsitic drain C, mixer cgs, routing etc.) before you lost 3dB gain, and this would still provide better load than a spiral L & Cload at 400MHz with much less area penalty.

2) To get the simulation right, you need to load the LNA with a representative impedance for the mixer Zin. If the LNA to mixer interface is totally on chip and the mixer input is a gate, then you need to load your LNA output with a capacitor in parallel to a port2 with resistance >> LNA tank impedance (i.e something like 100k). Doing an S11 on the mixer will tell you how to load the LNA. If you were to just slap 50 ohms across the output, you will not get any gain....

cheers
aw

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eng

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Re: Output impedance matching LNA 400MHz
Reply #2 - Dec 2^nd, 2006, 2:54pm

Hi ACWWONG,

Thanks for your nice answers. I followed your suggestion by swapping the inductor (~50 nH) with a resistor (~ 300 ohm) since there is not much IR drop on res due to the very low drain current. This saved huge area. The spectre sp simulation says that noise figure degenerated 0.3dB, s21 is almost same. However the voltage gain (after pss analysis) is around 0 dB while it was around 8.6 dB with inductor. Do you think that this is something expected? What is the reasonable explanation of this drop? Why do we care about voltage in LNAs?

Thanks

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aaron_do

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Re: Output impedance matching LNA 400MHz
Reply #3 - Dec 3^rd, 2006, 1:45am

If you're using PSS analysis for voltage gain, its possible that you're seeing gain compression. If you have 300 ohm and say 1 mA DC current then you're DC drop is only 300 mV. So that should be you're peak amplitude at the output (roughly). Also 300 ohm seems quite small compared to the output impedance of the transistor or the input impedance of a mixer (depends). Also in general I think for CMOS you should ask yourself why do we care about power, since the MOSFET is a voltage sensing device.

Aaron

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ACWWong

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Re: Output impedance matching LNA 400MHz
Reply #4 - Dec 3^rd, 2006, 10:12am

eng wrote on Dec 2^nd, 2006, 2:54pm:

Thanks for your nice answers. I followed your suggestion by swapping the inductor (~50 nH) with a resistor (~ 300 ohm) since there is not much IR drop on res due to the very low drain current. This saved huge area. The spectre sp simulation says that noise figure degenerated 0.3dB, s21 is almost same. However the voltage gain (after pss analysis) is around 0 dB while it was around 8.6 dB with inductor. Do you think that this is something expected? What is the reasonable explanation of this drop? Why do we care about voltage in LNAs?

hi eng,
i think if NF is hardly different and S21 is the same (and you're not changing port Z), the only reason i can think which is causing your gain loss is as aaron_do suggested... i.e. compression. So re-do you pss/transient analysis check if your signals are limiting, or just reduce the input signal power and re-sim. If this is not the reason, i can only think that your simulation setup is somehow incorrect.
Also as an RFIC designer i ALWAYS think in voltage gain (gm's in impedances) and voltage noise, and only rarely think of power when designing off-chip interfaces like LNA input or PA output. This is because the RF/analogue IC circuits amplify and process signal voltages (or currents) not powers.
cheers
aw

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