xter
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Posts: 6
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Hi,
I have verilogA code that works when run in cadence spectre, but not in Hspice. It's included as a subckt.
I) In attempting to debug this problem, I commented out everything except the port definitions. The code is saved in a file called stage5.va:
`include "constants.vams" `include "disciplines.vams"
module p_stage3_calib_model(VDD, Ph1, Ph2, Vrefp, Vrefn, Vip, Vin, D0M, D0L, S1, S0, Vop, Von); input Vip, Vin, Ph1, Ph2, Vrefp, Vrefn, VDD; output S1, output D0M, D0L; output Vop, Von; endmodule;
II) The instantiation looks like this:
yistage5 vdd1 Q1 Q2 vrefp vrefn vo6_p vo6_n d5l d5m SwitchRefHiStg5 SwitchRefLoStg5 vo5_p vo5_n p_stage3_calib_model
III) In the .lis file, the error reads like this:
During .hdl command processing, loading Verilog-A modules from './stage5.va'. hsp-vacomp: hsp-vacomp: Invoking the Verilog-A compiler for 'stage5.va' ** error ** During Verilog-A Device processing: Failed to compile the Verilog-A File, 'stage5.va'.
IV) And at the command prompt, I get this error:
ARnow: Undefined variable.
I am out of things to try to debug this problem. I thought if I slowly worked through the code, I could isolate this undefined variable, but I took out everything, and still get it.
Anyone have this error before?
Thanks! Xter
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