Hello Krishna
Thank you for response.
The problem is already resolved. File mentioned in include directive contained
Verilog-2001 syntax wich isn't supported by our tool.
I changed it and then import passed.
Concernig
Quote:whether the Reference library has all the necesary views like sch, symbol etc, for the gates
used in the verilog netlist
it's not really important as one can import verilog as functionnal view.
Moreover, the tool (Verilog-In) is capable to create view for each module contained in huge verilog source and
create symbol for each module.
Regards.
Pavel.