Designer’s Guide Community

Pavel

Senior Member

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Posts: 174
Lausanne/Switzerland

Verilog-In failed
Nov 27^th, 2006, 1:38am

Hello

Trying to import design coded in verilog (developed in PC-based design flow) using
Cadence Verilog-In facility I receive a number of the warning messages like this:

Warning! Code following `include command is ignored � � � � � � �[Van-CAICI] �
"/site/proj/src/mlx_topdig.v", 95:

I checked paths in `include directives. They are correct.

Best regards.

Pavel.

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krishnap Community Member Offline Posts: 55	Re: Verilog-In failed Reply #1 - Dec 11^th, 2006, 4:36am Hi Povel, Please check whether Reference Library is filled in correctly for the base cells, which are used in the verilog netlist. i.e, whether the Reference library has all the necesary views like sch, symbol etc, for the gates used in the verilog netlist. Thanks and regards , krishna
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Pavel

Senior Member

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Posts: 174
Lausanne/Switzerland

Re: Verilog-In failed
Reply #2 - Dec 18^th, 2006, 2:35am

Hello Krishna
Thank you for response.

The problem is already resolved. File mentioned in include directive contained
Verilog-2001 syntax wich isn't supported by our tool.
I changed it and then import passed.
Concernig
Quote:

whether the Reference library has all the necesary views like sch, symbol etc, for the gates
used in the verilog netlist

it's not really important as one can import verilog as functionnal view.
Moreover, the tool (Verilog-In) is capable to create view for each module contained in huge verilog source and
create symbol for each module.

Regards.

Pavel.

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zhong

Community Member

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Posts: 36
California , United States

Re: Verilog-In failed
Reply #3 - Dec 19^th, 2006, 10:55pm

Pavel,
If my guess is correct then you are using the IC5141 version older than USR4. The errors messages show that the default verilog parser is still using VAN instead of ncvlog . In USR4 the default paser is ncvlog then you will not see this error during verilogIn.

If you are using old version of IC5141 you can also turn the paser to ncvlog by setup skill variable in CIW schHdlUseNcvlogForVerilog = t

BTW, Besides verilogIn , The other way to bring the RTL or gate level verilog text INTO DFII lib is to run ncvlog compilation . for example
ncvlog -use5x -work my_d_lib -view module my_verilog_file.v

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Pavel Senior Member Offline Posts: 174 Lausanne/Switzerland	Re: Verilog-In failed Reply #4 - Dec 28^th, 2006, 4:41am Thanks
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