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array initialization in Verilog (Read 3551 times)

Pavel

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Posts: 174
Lausanne/Switzerland

array initialization in Verilog
Nov 29^th, 2006, 7:45am

Hello

For my test bench I need in 8-member array of 11-bit constants.
Only approach I found working is:

Code:

	reg �[10:0] �local_PWDN_etalon [0:7];

	initial begin
		local_PWDN_etalon [0] = �11'b00000011100;
		local_PWDN_etalon [1] = �11'b00000011000;
		local_PWDN_etalon [2] = �11'b00000011100;
		local_PWDN_etalon [3] = �11'b00000011100;
		local_PWDN_etalon [4] = �11'b11111111111;
		local_PWDN_etalon [5] = �11'b01111111011;
		local_PWDN_etalon [6] = �11'bx;
		local_PWDN_etalon [7] = �11'b00000011101;
	end

Is there a possibility to avoid using construction initial?

Regards.

Pavel.

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jbdavid Community Fellow Offline Posts: 378 Silicon Valley	Re: array initialization in Verilog Reply #1 - Dec 8^th, 2006, 11:20pm of course, you can define the values in a text file and do readmemh but its still probably in the inital block.. any verilog text book will have other ways of doing this.. Jonathan
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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: array initialization in Verilog Reply #2 - Dec 9^th, 2006, 10:03am Why do you want to avoid using initial? -Ken
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