bharat
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I am throwing the question: Whatever the spread I am seeing in MC simulation, the designer owe a part of it and major part goes to process inaccuracy. If all the transistors are in saturation, what else a designer can do. I am also seeing similar results in my op-amp while calculating voltage offset. The ratio of mean value to 3 sigma value is close to 150. Designer's task is to meet the specs for mean value and some percantage in the neighborhood of it. If the model is in a way that variation in L, W, Vth, overlapping cap, doping concentration is so much, how can really design can contain these variations and go for 'robust design'. If the expectation is that all those variations should be taken as design challenge, I am afraid if I am agree. Also, for example, if the model considers that there may be mismatch in the device dimension, shouldn't they account for that all the devices are laid out in common centroid fashion for perfect matching with dummy devices to avoid any distortion in the devices while polishing in the process. (because I ran pre-layout MC sims) In addition, is it worth to burn the night oil for a designer to design for such a device which has worst L, W, Vth, overlap cap, doping conc mismtach in one device which may be one in millions. Isn't it overly pessimistic and far from real life scenario. Also, what do you say for die to die variation. How can one contain it? Please comment if I shouldn't think this way as a Designer.
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