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Any CDR model by Verilog-A (Read 5432 times)

neoflash Community Fellow Offline Mixed-Signal Designer Posts: 397	Any CDR model by Verilog-A Dec 24^th, 2006, 8:39pm Hope could view it as reference to write mine, thanks.
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Any CDR model by Verilog-A Reply #1 - Jan 2^nd, 2007, 4:22am What's a CDR?
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Frank Wiedmann Community Fellow Offline Posts: 678 Munich, Germany	Re: Any CDR model by Verilog-A Reply #2 - Jan 2^nd, 2007, 4:55am Clock and Data Recovery, probably.
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jbdavid

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Posts: 378
Silicon Valley

Re: Any CDR model by Verilog-A
Reply #3 - Jan 20^th, 2007, 8:26pm

if you can use Verilog-AMS its probably better..
The main trick in my first one was to understand they type of CDR..
so I used a normal PFD for the "lock to reference" phase, when that is locked, the CDR gets a signal, that switches the control to the data channel Phase detector.
The model I have references the design of our IP vendor, so I can't share it. Just these general concepts.

jbdavid
Mixed Signal Design Verification

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