But still I am facing same problem,
If you consider CS amp,
load as pmos current mirror circuit (m2 and m3) and nmos (m1),...(m2 diode connected)
Here if you simulate this amp ckt,I am getting below mention result :
After plotting 'gain and frequency plot'
1. m1 in sat and m2 in sat --> 35 db gain.
2. m1 in linear and m2 in sat --> 12 db gain.
3. m1 in sat and m2 in linear --> 12 db gain.
As we have discussed earlier,it is very difficult to get both transistors in sat region without f/b.
But in two stg opamp when you are connecting this CS amp as a second stage,it has a input from
o/p of differetial amp circuit.
As this differential amp having large o/p range variation,it wont able to keep CS amp's both transistors in sat
region (it results in gain reduction).
Above dicussion regarding open loop configuration.
Then how we can get correct open loop gain?
Plz,help me out.
Thanks.