Won
Junior Member
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Posts: 15
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Hi, Folks I have a question about LDO design Using 0.6um CMOS process, I try to design LDO which is available to drive 100mA. I designed error amplifier which has 70dB gain and 10MHz bandwidth. And I calculated the size of pass device. K’=42.4uA/V^2, Vdropout=Vdsat=Vgs-Vth=0.2V (W/L)=2*Ids/(K’*Vdsat^2)=118,371 So, (W/L)=(71mm/0.6um) The size of pass device is too big!! Am I correct????
Anyway, I keep designing with following spec. Supply voltage=3.3V, Output voltage=3V, reference voltage = 1.2V Quiescent current of feedback network resistors is 5uV. Feedback network resistors are 240K, 360K each.
Another question is DC analysis with load current condition. When I try to do DC analysis with full load current (100mA), pass device operates in the saturation region. It looks fine. However, for no load current (0A), pass device operates in the cutoff region. Could you please tell me what I did wrong? Do I need bypass current in order to make pass device operate in saturation region?
Well, this is first time for designing LDO. Could you please give me some tips?
Best regards,
Won
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