Hi,

I think the .sdf file is a back-annotation file for gate-level simulation of verilog or VHDL. So you need not import the verilog netlist to a cadence composer. In some HDL simulator, the .sdf file is read and the post-layout timing information is annotated at each path and gates, flip-flops, etc.

Yawei

I guess what you were asking is to import SDF to Cadence Virtuoso DFII database ? And  you have imported Verilog gate level netlist into the DFII.

Actually you don't need to "import SDF" to be "DFII database" .  SDF file is a standard text, you can directly backannotate SDF text file to your Verilog gate level netlist during ncelab stage  either in command mode or GUI mode.

Here is what you need to do ..
For example , you have raw SDF file  "my_sdf.txt"

1. run ncsdfc  to generat compiled SDF file
    ncsdfc my_sdf.txt   ---> generat my_sdf.txt.X  which is compiled SDF file

2. Prepar  SDF command file say MY_SDF_CMD.txt , for example
 COMPILED_SDF_FILE = "PATH_TO_YOUR_SDF_FILE/my_sdf.txt.X" ;
 SCOPE = top.I0.I1 ;      
           ----- This means that your verilog gate level block is top.I0.I1 in top level design context .

 ....

3. In AMS-ADE or AMS-HED GUI
        In ncelab options -> SDF command field ,
              please fill   path_to_your_sdf_command_file/MY_SDF_CMD.txt



So that SDF will backannotate to the verilog gate level block ..

Hope this helps ..
Zhong

In fact , My previous reply did address how to backannotate SDF to the verilog code in DFII schematic. It should address your question.  For example of my SDF cmd file ..
 top.I0.I1  
top is schematic
 top.I0 is shematic
   top.I0.I1 is verilog module (gate level netlist) for SDF backannotation to .

This is way I use to backannotate SDF to analog-mixed design in DFII GUI all the time .

Hope this helps ..