sugar
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topquark and Frank Wiedmann,
thank you for your replies. Using calculator is not a good method for my case, because I need an AC source, not manipulated simulation result.
I have tried to use verilog-A to model it, but the results are strange. Following is a simple verilog-A model, just for test.
module ac_src(freq, out); input freq; output out; electrical freq, out; real varOut; analog begin varOut = V(freq); V(out) <+ ac_stim("ac", varOut); end endmodule
In above model, freq is a input pin whose value is proportional to simulation frequency.
The simulation results alway show
mag(VF("/out")) = 0 phase(VF("/out")) = 0
what's wrong with my model?
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