Thank you for the lone reply to my question!
I wanted to know how many analog designers perform the fabled/mythical 'top level simulation' in order to determine circuit level specs. To ask the same question in a different way: plot a graph with Y axis as manufacturing yield and X axis as a composite figure-of-merit, consisting of design complexity, power diss, die size, ... How many design managers have some sense of such a graph before making design choices?
M.G.Rajan
www.eecalc.com