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LDO design (Read 3152 times)

rf_jay New Member Offline Posts: 7	LDO design Jan 28^th, 2007, 9:44pm Can we design a stable LDO from 7volt input to 3.3volt output in microwatt range. can we use the onchip cap for this application? if yes how big cap? thanks in advance, jay.
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: LDO design Reply #1 - Jan 30^th, 2007, 1:45pm Jay: The answer is yes.... but thats not a very useful answer is it? Got any specifics on such a design that you need to cover? The question is pretty global, so you are not going to get a lot of useful answers IMHO.
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rf_jay New Member Offline Posts: 7	Re: LDO design Reply #2 - Feb 2^nd, 2007, 3:40am Thanks for the reply. The chip has around 10k digital logic. the supply for those is from the output of this LDO. The chip has limitation on number of pins and hence using external cap. can you please furnish me some docs/pdfs of examples where in capacitor less LDO's are tested on chip. Having these docs will be great. regrds. jay.
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ywguo

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Posts: 943
Shanghai, PRC

Re: LDO design
Reply #3 - Feb 7^th, 2007, 1:17am

Hi, jay,

I designed a LDO w/o external cap for a small digital circuit and an EEPROM. The simulation proved large transient ripples when the loading (digital circuit) were operating.

I think the first problem is to model the transient current supply of a 10K gates digital circuit.

The second problem is a circuit topology. The conventional topology often needs very huge external cap.

Best regards,
Yawei

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