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VerilogANovice New Member Offline Posts: 9 Mountain View	"Static" variable in VerilogA Jan 30^th, 2007, 12:47am Can there be "static" variable (like those in C) in Verilog A? I want my device model to behave differently when I sweep voltage from 0 to 5V and from 5V to 0V, so I want the device model to kinda remember what has happened to it before. Is there any way to do so? Thanks!
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Geoffrey_Coram

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Massachusetts, USA

Re: "Static" variable in VerilogA
Reply #1 - Jan 30^th, 2007, 4:28am

A variable that does what you're talking about is often called a "hidden state" variable (and causes trouble for some analysis types in some simulators).

Code:

`include "disciplines.h"
module hyst(in, out);
inout in, out;
electrical in, out;
real hyst_state;

analog begin
  if (V(in) < 2) hyst_state = 0;
  if (V(in) > 4) hyst_state = 1;

  V(out) <+ hyst_state;
end
endmodule

This should demonstrate what you want; try it both in a dc sweep of the voltage driving "in" and also with a transient -- say sine wave -- that goes from 0 to 5.

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VerilogANovice New Member Offline Posts: 9 Mountain View	Re: "Static" variable in VerilogA Reply #2 - Jan 30^th, 2007, 4:49pm Thanks a lot! It's exactly how I want it to behave. Would you please explain how it works? Thanks!
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Geoffrey_Coram

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Re: "Static" variable in VerilogA
Reply #3 - Jan 31^st, 2007, 3:55am

The language specifies that all variables are initialized to zero at the start of the simulation. Each time the module is evaluated (for the time=0 dc solution and at each timepoint) the voltage V(in) is compared to the threshold, and if it meets one of the conditions, the appropriate value is assigned to hyst_state. The value of hyst_state is otherwise persistent across timepoints.

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Ken Kundert

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Re: "Static" variable in VerilogA
Reply #4 - Jan 31^st, 2007, 10:01am

Verilog modules are conceptually quite different than the functions you will find in a traditional programming language like c or c++. Modules are intended to model a piece of hardware, and as such are not 'called', but rather 'instantiated'. Thus, the module always exists and is active, meaning that it is constantly monitoring its inputs and producing outputs. In addition, the local variables in a module retain their values over time. As such they are considered state variables and are similar to the 'static variables' you will find in c or c++. There is no equivalent to the 'automatic variables' of c or c++ within a Verilog module.

Here when I say Verilog I mean all forms of Verilog, including Verilog-A and Verilog-AMS.

-Ken

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