Ken Kundert
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Verilog modules are conceptually quite different than the functions you will find in a traditional programming language like c or c++. Modules are intended to model a piece of hardware, and as such are not 'called', but rather 'instantiated'. Thus, the module always exists and is active, meaning that it is constantly monitoring its inputs and producing outputs. In addition, the local variables in a module retain their values over time. As such they are considered state variables and are similar to the 'static variables' you will find in c or c++. There is no equivalent to the 'automatic variables' of c or c++ within a Verilog module.
Here when I say Verilog I mean all forms of Verilog, including Verilog-A and Verilog-AMS.
-Ken
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