Visjnoe
|
Dear all,
following up on a previous post I made, I'd like to re-discuss the integration interval for the phase noise of a CLK which is delivered to an ADC.
In the previous discussion I stated (and other people) that the phase noise should be integrated upto FCLK/2, the idea being that higher frequency jitter/noise cannot be observed in 1 CLK period.
Concerning the 'observation', I think the statement is correct. However, the CLK's edges actually 'undersample' the high frequency noise, leading to noise folding. Thus, also noise above FCLK/2 can appear 'in band'.
Basically, I now think this noise can have a contribution to the overall jitter of the ADC CLK. So, when designing an oscillator for an ADC, the phase noise integration's interval upper limit is not FCLK/2.
Any comments are more than welcome...
Kind Regards
Peter
|