Dear all,

following up on a previous post I made, I'd like to re-discuss the integration interval for the phase noise of a CLK which is delivered to an ADC.

In the previous discussion I stated (and other people) that the phase noise should be integrated upto FCLK/2,
the idea being that higher frequency jitter/noise cannot be observed in 1 CLK period.

Concerning the 'observation', I think the statement is correct. However, the CLK's edges actually 'undersample' the high frequency noise, leading to noise folding. Thus, also noise above FCLK/2 can appear 'in band'.

Basically, I now think this noise can have a contribution to the overall jitter of the ADC CLK. So, when designing an oscillator for an ADC, the phase noise integration's interval upper limit is not FCLK/2.

Any comments are more than welcome...

Kind Regards

Peter

Define "phase noise" Stheta(f) as the power spectral density of the discrete sequence:
   theta_n := 2Pi f0 ( t_n - n T ) , n = 1 ..
where t_n are clock transition times, and T := 1/f0 is the nominal clock period.
Stheta(f) is simply the power spectral density of absolute jitter expressed in radians.
Here, the upper integration limit should be f0/2, because this is psd for a discrete sequence.

To predict the effect of clock jitter on ADC performance, will need to consider that clock phase noise is colored by the PLL, and the subsequent discrete filtering operation to be performed after ADC.