HFG
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Posts: 5
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Hello All,
Iam simulating schematic level simulations of phaselocked loops. I run PSS and Pnoise to generate the phaseNoise plot. Regardless of what type of PLL i design i get a phase noise slope of -10dBc/hz per decade but its suppose to be -20dBc/Hz per decade. I am pretty sure its not a circuit issume but a simulator problem. Will incorrect settings result in the wrong profile of the phase noise ? anyone run into this issue before ?
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