Hello,

Is there a possibility to import "System Verilog" code?

Regards

Pavel.

As cell in Library Manager to be used as Test Bench.
I tried already Verilog-In. But in System Verilog there are constructs that aren't supported by Verilog/Verilog 2001 parser.
So import didn't pass.

Regards.

Thanks Zhong,

It worked. Cell was created with module view.

Regards.

Pavel.

There is no special env varible today in GUI flow to handle SystemVerilog.
The problem you have is that ,
    you compile the SystemVerilig text into DFII view use -sv  --- works fine
After that ,
    In AMS-ADE or AMS-HED , the GUI flow will RE-COMPILE the SystemVerilog  without -sv option.
    ---- This explains why you have problem.

The workaround is to
1. Compile all your SystermVeriliog to a exclusive lib which only have SystermVerilog
    for example
     ncvlog -use5x -sv -work my_systemVerilig_lib  my_systemVerilog_file.sv

2. In GUI flow (either AMS-ADE or AMS-HED)
   add my_systemVerilog_lib in the  "exclude libs list for compilation"   . You can find this field in the Compilation option form .
   This will avoid GUI re-compile the systemVerilog without -sv option.

BTW, if you change your IUS version , You need to re-do
  ncvlog -use5x -sv -work my_systemVerilig_lib  my_systemVerilog_file.sv
to ensure the version of IUS you are using in command compilation is same as GUI flow.

Hope this helps ..

Zhong

Pravel,
Your understand that corretly. As of today, GUI flow default does not issues the -sv for the compilation.

However you can add -sv in the additional compilation option in GUI . Now the issues will be -sv will be apply for all the text file (verilog/SystermVerilog/verilog.vams (generated from schematic) , the problem then is NC  does not allow you have co-existence of   -sv -ams option in the same ncvlog compilation line. This will cause the compilation failure on verilog.vams netlsit which generated from schemaitc.

What you can do is to
1. Once you have changed the SystemVerilog . Compile that from Command line
or
2. Add -sv in the GUI compilation option ,  
  then surgically compile the SystemVerilog cell only in HED
  after that remove -sv from GUI option, add the systemVerilog lib in the Exclude list
  compile all

I would suggest you to go with solution 1>. It's much esaier than 2.


Zhong