Hi,

I have a question about making VCO stop oscillating.

When doing 3-stage VCO design, I want to verify that - when low frequency gain of the delay cell is smaller than 2 (i.e. 6.02dB), the VCO will stop oscillating because the insufficient gain.

I run AC simulation on one delay cell (with parasitic loading), tuned the bias voltage to make it gain=5.45dB (<6.02dB). Then, I applied the bias voltage on VCO, however, the VCO doesn't stop oscillation.

The DC operating point is set at where the input common mode close to output common mode.

I don't know what I missed in the simulation, please help, thank you!

assume one-stage transfer function is A0/(1+S/w0), three stages would be H(s)=A0^3/(1+S/w0)^3

To achieve oscillation,
1) phase shift of each stage is 60deg. i.e. fosc=f0 * sqrt(3)
2) at oscillating freq., |H(s)|>=1. Applying condition 1), min. A0=2 (i.e. 6.02dB)

I wonder if my AC simulation setup is not correct. For the inputs to the diff. pair, vin is connected to DC common mode voltage, vip is connected to an AC source (with DC common mode voltage).  or should I connect both inputs vin and vip to two seperated AC sources?

Thanks,
YeeQ

Just for some cross checks:
Does the oscillator oscillate at the same frequency that resulted in 60deg phase margin when making the AC sim?

I think that analisys may not correlate because the AC is computed from the small signal analisys at a given DC point, and nomally ring oscillators have big swings and cannot be treated as operating in a linear region,

Regards,
Humberto

Since the gain used here is only slightly lesser than 2, any disturbance anywhere (due to noise) would result in ringing for some period of time. Although in the small signal sense this oscillation isn't self-sustaining, the inverters pick up this disturbance and blow it up into a large-signal full-scale oscillation. So, I guess, your oscillator can potentially oscillate unless the gain of each stage is reduced well below 2.