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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › Instantiating a built-in model

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Instantiating a built-in model (Read 3199 times)

VerilogANovice New Member Offline Posts: 9 Mountain View	Instantiating a built-in model Feb 25^th, 2007, 3:03am Hi all, Can I instantiate a built-in MOS model from Verilog-A? Thanks
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zhong Community Member Offline Posts: 36 California , United States	Re: Instantiating a built-in model Reply #1 - Feb 25^th, 2007, 11:52pm You can..
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VerilogANovice New Member Offline Posts: 9 Mountain View	Re: Instantiating a built-in model Reply #2 - Feb 26^th, 2007, 12:39am Do you know how to do that in HSPICE? I am not sure how I can read in the model card in Verilog-A.
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Instantiating a built-in model Reply #3 - Feb 26^th, 2007, 5:23am The Verilog-AMS LRM does not specify how one defines model cards -- or the "library" for resolving model references -- in a Spice simulator. You'd need to check with an application engineer from Synopsys to find out how this works in HSpice.
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