I found approach how to detect bus activity in analog process.
It's sufficient to create additional clock that senses whole necessary digital activity,
and then employ this clock in analog process.
Code: electrical i1u_n1, i1u_p1, i2u_n1, i2u_n2, i2u_n3, i2u_n4, i2u_n5, i3u_p1, vbn1, sup;
logic en;
logic [3:0] Itrim;
reg event_clk = 0;
real i_total;
localparam i0 = 1u;
localparam di = 100n;
always @ (en or Itrim) event_clk = ~event_clk;
analog begin
@(posedge event_clk or negedge event_clk)
i_total = (en)?(i0 + (Itrim[0])?di:0.0 + (Itrim[1])?2*di:0.0 + (Itrim[2])?4*di:0.0 - (Itrim[3])?4*di:0.0):0.0;
I(i2u_n1) <+ i_total;
I(i2u_n2) <+ i_total;
I(i2u_n3) <+ i_total;
I(i2u_n4) <+ i_total;
I(i2u_n5) <+ i_total;
I(i1u_n1) <+ i_total/2.0;
I(i1u_p1) <+ - i_total/2.0;
I(i3u_p1) <+ - i_total*1.5;
$bound_step(100n);
end
But simulation results shows something strange (please, see the picture).
1. It seems that i0 isn't taken into account.
2.
i_total behavior doesn't correspond to formula in analog process.
I commited some mistake in my code or this is a simulator bug?
Regards,
Pavel.