Well, you end up with more capacitors on the chip, which can increase the amount of coupling between signals. Say you have (sideways view):

------
       --------
                 -------

where the top and bottom shapes are routing, and don't overlap. Without the middle dummy fill (if that's what it is), there would be a much smaller capacitance between the two and bottom shapes, than if the top couples to the dummy plate, which then couples to the bottom routing.

But of course, the dummy fill is to help with planarisation and so on, which also helps improve yield. So there are pluses and minuses!

Andrew.

Modern CMOS processes were using Chemical Mechanical Planarization
(CMP), for that reason floating metal is used to reach a defined
metal density for a given window over the chip area.
This metal often is called 'dummy metal' or 'metal filling'.
The same applies also for poly.

But Andrew is right, as always, you have to consider where
this dummy metal should be placed to not increase coupling
capacitance in sensitive blocks.
Often the placement of dummy metal is done through a DRC tool
on a script approach which also allows you to place exlude layers
for dummy metal insertion blockage around sensitive areas of your chip.

But for floating vias your DRC should flag an error.

Bernd