vivkr
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Dear Yawei,
The idle pattern is the response of a modulator to a DC excitation. On average, it should be at Fs/2 for a modulator with 1-bit quantizer, and also for a multibit one if I understand correctly because only 2 of the multibit levels are likely to be used (closest to the midlevel) unless you add randomizing dither to break the tones, which for a multibit delta-sigma is the standard way to remove idle patterns, and which does not work well for 1-bit quantizers.
However, the topic is relatively complex. I would recommend that you look at a book on introductory nonlinear systems. A good visualization is also offered in the book "Understanding delta sigma converters" by Schreier and Temes in Chapter 2 (See Fig. 2.23).
Regards Vivek
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