Hi Experts,

I'm a new born baby to this Elite Community!
Greeting to all of You!

I need your help in the below question! I believe this would be a best place for me to get an answer
When I design a SSTL_18 compliant IO buffer for differential signals,
JEDEC spec (JESD815) : Differential Signals (CLK/CLKB)cross points need to be in the range power/2 +- 0.125V.
This is for a  test condition :
 clk buffer --> r 20ohm --> tline (50ohm)---- -->
                                                                     |
                                                                     ---->across a 100ohm resistor ----> receiver
                                                                     |
clkbar buffer --> r 20ohm --> tline (50ohm) ---->

Here I believe depending on the receiver i/p load , the cross point is going to vary.

So To test this scenario, how are you people handling without a solid receiver load (this varies from customer to customer who uses this IO pad)


Sorry for being too specific in my question.

Can anyone throw me some lights on their experience to this scenario?