Hello,

Elaboration of design terminates with internal error (please, see the picture).
Message content make think that there is somewhere some inconsistency between bus widths that connect different blocks.

I made short survey of design architecture at first two levels and didn't find discrepancy.

Am I right in my supposition and how to find the cause of error if design is complex and tool doesn't give
any index of error location?

Regards,

Pavel.