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Dummy transistor and decoupling capacitor (Read 16550 times)

dandelion

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Dummy transistor and decoupling capacitor
Mar 13^th, 2007, 1:51am

Hi,
We have always add dummy transistors for the devices which need good matching.I wonder how to connect these dummy transistors. Connected the dran, source,bulk,gate together,then tied to VDD? Or Connected the dran, source,bulk,gate together,then tied to GND? Or put them floating? Or connect them as decoupling capacitor?

Always connecting them as decoupling cap have any risks?

I would be happy to hear your advice.

Thanks

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adesign Community Member Offline Posts: 73	Re: Dummy transistor and decoupling capacitor Reply #1 - Mar 13^th, 2007, 3:52am For pMOS connect drain, gate, source, bulk to VDD. For nMOS connect these to ground.
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dandelion Community Member Offline Posts: 98	Re: Dummy transistor and decoupling capacitor Reply #2 - Mar 13^th, 2007, 5:34am Always connecting them as decoupling cap have any risks? It is encouraged to do this? Thanks
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Croaker Senior Member Offline Posts: 235	Re: Dummy transistor and decoupling capacitor Reply #3 - Mar 19^th, 2007, 9:06am For dummy transistors, is there any point in making the length greater than minimum, even if the MOSFETs they are shielding are longer than minimum?
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: Dummy transistor and decoupling capacitor Reply #4 - Mar 21^st, 2007, 7:19pm dandelion wrote on Mar 13^th, 2007, 5:34am: Always connecting them as decoupling cap have any risks? � It is encouraged to do this? Thanks No risk if you keep the gate-source voltage and gate-drain voltage not greater than the supply voltage.
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qiushidaren Community Member Offline I am a lovely MOSFET! Posts: 86 Chengdu	Re: Dummy transistor and decoupling capacitor Reply #5 - Mar 22^nd, 2007, 8:50pm Why not put them floating, I think doing this may be better.
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krishnap

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Re: Dummy transistor and decoupling capacitor
Reply #6 - Mar 23^rd, 2007, 2:47am

One of the terminals could be connected to the adjascent active transistor and gate and other terminal is connected to
ground or power based on NMOS 0r PMOS respectively.
As Croker suggested dummy device can be of minimum length.
Floating device may not be advisable, and it is better to tie all the devices to some bias ..

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avlsi

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Re: Dummy transistor and decoupling capacitor
Reply #7 - Mar 23^rd, 2007, 4:33am

dummy is helpful only when u need good matching. generally, I connect gate of the PMOS(dummy) to VDD, so that its OFF always and NMOS vice versa.

In my chip, I shared the drain or source of dummy transistor with the real transistor to remove the etching problem during fabrication. This really helps a lot in diff apms in reducing offset.

Winners never Quit,Quitters never Win

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Croaker

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Re: Dummy transistor and decoupling capacitor
Reply #8 - Mar 23^rd, 2007, 8:10am

krishnap wrote on Mar 23^rd, 2007, 2:47am:

As Croker suggested dummy device can be of minimum length.
Floating device may not be advisable, and �it is better to tie all the devices to some bias ..

I was actually asking...I think it can be minimum length in all cases, but if anyone knows differently, please let me know!

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chase.ng

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Re: Dummy transistor and decoupling capacitor
Reply #9 - Mar 23^rd, 2007, 10:13am

Hi all,

A question over here, if the PMOS or NMOS dummy has shared drain/source with other device and the gates are tied to the respective power supply to shut them off, will any ESD event like the CDM break those gates and short those devices since those gates are directly connected to pads? I once do that in a test chip which was never subject to ESD test, I wonder is that ok for production chip, anyone has experience on this?

Thanks and Regards,
chase

Chase

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krishnap Community Member Offline Posts: 55	Re: Dummy transistor and decoupling capacitor Reply #10 - Mar 24^th, 2007, 3:54am Hi Chase, Some of the production chips had this configuration, where gate and other terminal connecting to power or ground. Regards, Krishna
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chase.ng Community Member Offline Posts: 77 penang/malaysia	Re: Dummy transistor and decoupling capacitor Reply #11 - Mar 26^th, 2007, 6:28pm Hello Krishna, Thanks for the info. Are those fets ESD protected in any other way? Or they just wired the gates to power supply? Anyone else had experience on this? Thanks and Regardsm Chase
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ywguo

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Shanghai, PRC

Re: Dummy transistor and decoupling capacitor
Reply #12 - Mar 26^th, 2007, 8:22pm

chase.ng wrote on Mar 26^th, 2007, 6:28pm:

Hello Krishna,

Thanks for the info. Are those fets ESD protected in any other way? Or they just wired the gates to power supply?

Anyone else had experience on this?

Thanks and Regardsm
Chase

I think the power supply pads have ESD protection. So don't worry about ESD although we often wired the gates to power supply.

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ywguo

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Re: Dummy transistor and decoupling capacitor
Reply #13 - Mar 26^th, 2007, 8:32pm

Croaker wrote on Mar 23^rd, 2007, 8:10am:

I was actually asking...I think it can be minimum length in all cases, but if anyone knows differently, please let me know!

Good question. I want to know the answer, too. One simmillar question, the above idea is very useful for capacitor matching. I use very narrow metal as dummy surrounding those caps. However, I know some big companies use dummy cap very generously. For eg., in a 1.5bit/stage pipelined ADC, each MDAC has 4 unit caps totally. They use 12 more unit caps as dummy cell. The former 4 unit caps are put in the center, while the other 12 are put surrounding them. They construct a 4x4 unit cap array and consumes much more area.

Anyway, I want to reduce the area as more as possible. Any comments are appreciated.

Thanks
Yawei

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Croaker Senior Member Offline Posts: 235	Re: Dummy transistor and decoupling capacitor Reply #14 - Mar 27^th, 2007, 6:20am Regarding the caps, I think you are OK as long as there is some surrounding metal. No need to put big dummy caps around the edges.
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