Pavel
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Hello
I didn't find in documentation how can I simulate veriloga/verilogams models in DC. I tried following approach: 1. created veriloga model 2. created symbol for it 3. created schematic testbench - dc stimuli + model 4. invoked ADE 5. in ADE changed simulator for ams 6. choose dc analysis in ADE
But there are no any parameter to specify - no source to sweep, start/stop/step, etc.. (please, see the picture)
Regards,
Pavel.
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