I am trying to figure out a way to do the entity/architecture concept that VHDL has.

I can see a way based on naming conventions or the preprocessor, but I really prefer something officially supported by the language.

It is for a multi-tool suite, not all simulation.  There are several architectures per entity,  The intent is to have a mechanism for automatically choosing architectures.  How to choose is not the problem.  There are cases where more than one architecture can be used at the same time, may be selected by a "binning" mechanism, or may be dynamically chosen during a simulation, or by a non-simulation application.

VHDL has the needed features, language defined.  We would rather use Verilog, but need this feature.

The pressing need is for a multi-tool environment, with about 10 tools interacting.  Only 2 of them are simulators.

VHDL has the concept of an "entity" which has one or more "architectures".  In verilog, these concepts are combined into a "module".  The "entity" specifies the interface, much like a function prototype in C.  The "architecture" implements it.  The body of an "architecture" is equivalent to the body of a "module".

The important feature is that there can be several "architectures" and a language supported way to specify it.

In simulation, one use of separate architectures might be a structural and behavioral model of the same entity, or possibly a fast model and an accurate model, or a nice model that guarantees convergence, used to start a homotopy to an accurate model that might not be so well behaved.

entity FOOBAR is
....
end entity

architecture yellow of FOOBAR is
....
end architecture

architecture green of FOOBAR is
....

architecture red of FOOBAR is
....

architecture blue of FOOBAR is
....

I can refer to FOOBAR, and have which one automatically selected somehow, or I can refer to FOOBAR(blue) or something like that.

I suppose it could be done in Verilog with the preprocessor:

`ifdef yellow
module FOOBAR
....
`else
`ifdef green
module FOOBAR
....

...
`endif
`endif

but we want to be able to select more than one, perhaps to compare one to another.

Another approach could be multiple modules with a naming convention

module FOOBAR_yellow
....

module FOOBAR_green
....

.. and we could have a "proprietary" way to map and select.

But we don't want proprietary.  We want to support industry standards, and make the best use of them.  We have existing tools in Verilog and would like to stick with it.  Our user community has indicated a strong preference for Verilog over VHDL.

So ..

Is there an official language specified way to do this?  (I can't find it.)

Is there a precedent for naming conventions or something like that?

Is there a better way?

Actually, probably a better/more standard way is to use the "generate" construct.  This is covered in 12.4.2 Conditional generate constructs in the 1364-2005 LRM.  There's actually an example that instantiates an OR or an AND depending on parameter values.

I'm not sure if the idea of a "configuration"  which I use all the time with spectre & AMS  helps..
with-in the tool you can have multiple views of an object.. (ie a schematic or veriloga model or verilogams model or functional model.. depending on the tool you are using, the views its compatible with, and the search order you list, some views are used by default - the configuration allows you to specify the view you want for the cases where the view is not the default..
generally I leave the schematic as the default, then set the config to use the veriloga view..  where I want that to be used..
--
If there is an elaboration step defined in verilog ams, the configuration is the information  used by the elaborator to choose the view to use when more than 1 view type exists.. but this might be specific to the Cadence implementation..

Altermatively - one might use a "view binding" property on an instance declaration..
(* string view_binding = "analogfunctional"; *)

each view of the same block would have the same module name, but a different view name (can be id'd by the file extension..
.va = veriloga .vaf = analogfunctional .vb = behavioral .vab = analogbehavioral .vs = structuralnetlist (ie from synthesis)
.vas = analogschematic  etc..

this sort of assumes the cadence NC compilation  model  where each file/module (and each view of that module) is compiled as its own object in the binary library, and then the linker(elaborator) determines which object to use.. as directed by the configuration (sort of a make file?)

-- but the basic idea in verilog is to let something outside the module  itself control which flavor of instances are used during the simulation.

so the module defined the interconnection of the blocks of your design, while the configuration determines which models (views ) of those blocks are going to be used..

the cadence model makes library.cell:view as a directory structure in the filesystem..
for a "flat" file structure the extension is used as a view identifier..
(note this works with Nedit as a text editor as well as the syntax patterns depend on the file extension.. )

If I keep going I'm rambling (if I'm not already..)
jbd